/*
 * config_ROM_HW.h
 *
 *  Created on: Aug 31, 2013
 *      Author: Ken Arok
 *
 */

/**
 * \brief ROM Configuration Management.
 *
 * This memory mapping is for specific application configuration.
 * Be aware, the structure of ROM must be as described below.
 * -----------------------------------------------------------
 * Block |	Sector	|	Size	|		Used by
 * -----------------------------------------------------------
 *   1	 |	  1		| 	1KB		|	Hardware configuration
 *   1	 |	2 - 10	| 	9KB		|	Device configuration
 *   1	 |	10 - 31	| 	21KB	|	Application
 *   1	 |  32		|	1KB		|	System configuration
 *   2	 |  1 - 32	| 	32KB	|	Reserved
 *   3	 |	1 - 32	| 	32KB	|	Reserved
 *
 * Copyright (c) 2013 PT Hanindo Automation Solutions. All rights reserved.
 *
 */

#ifndef CONFIG_ROM_HW_H_
#define CONFIG_ROM_HW_H_


/* Base address of ROM used for RAM Pointer. */
extern void *ROM_Base_Block1;
extern void *ROM_Base_Block2;
extern void *ROM_Base_Block3;
extern void *ROM_Base_Block4;
extern void *ROM_Base_Block5;


/* Start ------------------------ General definition and macro. ------------------------ */
/* Size of each block. */
#define ROM_BLOCK_SIZE					(32 * 1024)
/* Origin offset. */
#define ROM_ORIGIN_OFFSET				0

/*! \name Base address of each block from origin (offset 0).
 */
//! @{
#define ROM_BASE_ADDR_BLOK1				(ROM_ORIGIN_OFFSET)							//!> 1st block
#define ROM_BASE_ADDR_BLOK2				(ROM_BASE_ADDR_BLOK1 + ROM_BLOCK_SIZE)		//!> 2nd block
#define ROM_BASE_ADDR_BLOK3				(ROM_BASE_ADDR_BLOK2 + ROM_BLOCK_SIZE)		//!> 3rd block
#define ROM_BASE_ADDR_BLOK4				(ROM_BASE_ADDR_BLOK3 + ROM_BLOCK_SIZE)		//!> 4th block
#define ROM_BASE_ADDR_BLOK5				(ROM_BASE_ADDR_BLOK4 + ROM_BLOCK_SIZE)		//!> 5th block
//! @}

/* Do not use two last bytes of each block memory.
 * Already reserved for checking. */
#define RSV_WORD_BLOCK_OFFSET			(ROM_BLOCK_SIZE - 2)

/*! \name Offset address of each sector in the block.
 */
//! @{
#define ROM_SECTOR1_OFFSET				((1 - 1) * 1024)
#define ROM_SECTOR2_OFFSET				((2 - 1) * 1024)
#define ROM_SECTOR3_OFFSET				((3 - 1) * 1024)
#define ROM_SECTOR4_OFFSET				((4 - 1) * 1024)
#define ROM_SECTOR5_OFFSET				((5 - 1) * 1024)
#define ROM_SECTOR6_OFFSET				((6 - 1) * 1024)
#define ROM_SECTOR7_OFFSET				((7 - 1) * 1024)
#define ROM_SECTOR8_OFFSET				((8 - 1) * 1024)
#define ROM_SECTOR9_OFFSET				((9 - 1) * 1024)
#define ROM_SECTOR10_OFFSET				((10 - 1) * 1024)
#define ROM_SECTOR11_OFFSET				((11 - 1) * 1024)
#define ROM_SECTOR12_OFFSET				((12 - 1) * 1024)
#define ROM_SECTOR13_OFFSET				((13 - 1) * 1024)
#define ROM_SECTOR14_OFFSET				((14 - 1) * 1024)
#define ROM_SECTOR15_OFFSET				((15 - 1) * 1024)
#define ROM_SECTOR16_OFFSET				((16 - 1) * 1024)
#define ROM_SECTOR17_OFFSET				((17 - 1) * 1024)
#define ROM_SECTOR18_OFFSET				((18 - 1) * 1024)
#define ROM_SECTOR19_OFFSET				((19 - 1) * 1024)
#define ROM_SECTOR20_OFFSET				((20 - 1) * 1024)
#define ROM_SECTOR21_OFFSET				((21 - 1) * 1024)
#define ROM_SECTOR22_OFFSET				((22 - 1) * 1024)
#define ROM_SECTOR23_OFFSET				((23 - 1) * 1024)
#define ROM_SECTOR24_OFFSET				((24 - 1) * 1024)
#define ROM_SECTOR25_OFFSET				((25 - 1) * 1024)
#define ROM_SECTOR26_OFFSET				((26 - 1) * 1024)
#define ROM_SECTOR27_OFFSET				((27 - 1) * 1024)
#define ROM_SECTOR28_OFFSET				((28 - 1) * 1024)
#define ROM_SECTOR29_OFFSET				((29 - 1) * 1024)
#define ROM_SECTOR30_OFFSET				((30 - 1) * 1024)
#define ROM_SECTOR31_OFFSET				((31 - 1) * 1024)
#define ROM_SECTOR32_OFFSET				((32 - 1) * 1024)
//! @}

/* ROM Signature. */
#define ROM_SIGNATURE		(0x5A5A)

/* End ------------------------ General definition and macro. ------------------------ */



/* Start---------------------------- Hardware Configuration -------------------------- */

/*! \name Configuration for UART.
 */
//! @{

/* COM Setting Offset. */
#define ROM_COM_BAUDRATE_OFFSET			(0)
#define ROM_COM_DATALENGTH_OFFSET		(4)
#define ROM_COM_PARITY_OFFSET			(5)
#define ROM_COM_STOPBIT_OFFSET			(6)

/* ROM Length for UART setting. */
#define ROM_COM_SETTING_LENGTH			8

/* Offset of COM setting. */
#define ROM_COM1_SETTING_OFFSET			(ROM_BASE_ADDR_BLOK1 + ROM_SECTOR1_OFFSET)
#define ROM_COM2_SETTING_OFFSET			(ROM_COM1_SETTING_OFFSET + ROM_COM_SETTING_LENGTH)
#define ROM_COM3_SETTING_OFFSET			(ROM_COM2_SETTING_OFFSET + ROM_COM_SETTING_LENGTH)
#define ROM_COM4_SETTING_OFFSET			(ROM_COM3_SETTING_OFFSET + ROM_COM_SETTING_LENGTH)
#define ROM_COM5_SETTING_OFFSET			(ROM_COM4_SETTING_OFFSET + ROM_COM_SETTING_LENGTH)
#define ROM_COM6_SETTING_OFFSET			(ROM_COM5_SETTING_OFFSET + ROM_COM_SETTING_LENGTH)
#define ROM_COM7_SETTING_OFFSET			(ROM_COM6_SETTING_OFFSET + ROM_COM_SETTING_LENGTH)
#define ROM_COM8_SETTING_OFFSET			(ROM_COM7_SETTING_OFFSET + ROM_COM_SETTING_LENGTH)
#define ROM_RS485_SETTING_OFFSET		(ROM_COM8_SETTING_OFFSET + ROM_COM_SETTING_LENGTH)
#define ROM_TTL_SETTING_OFFSET			(ROM_RS485_SETTING_OFFSET + ROM_COM_SETTING_LENGTH)
// ------- 10 x 8 bytes = 80 bytes

#define ROM_COM_SETTING_SIZE	80

//! @}

/* Next Offset after COM setting. */
#define ROM_NEXT_OFFSET_AFTER_COM_SETTING	(ROM_BASE_ADDR_BLOK1 + ROM_COM_SETTING_SIZE)


/*! \name TCP/IP configuration.
 */
//! @{

/* ROM LENGTH for TCP/IP Setting. */
#define ROM_TCPIP_IP_ADDR_PARTIAL_LENGTH		1
#define ROM_TCPIP_SUBNET_MASK_PARTIAL_LENGTH	1
#define ROM_TCPIP_GATEWAY_PARTIAL_LENGTH		1
#define ROM_TCPIP_DNS_SERVER_PARTIAL_LENGTH		1
#define ROM_TCPIP_CONF_AUTOMANUAL_LENGTH		1

/* Offset of TCP/IP setting. */
#define ROM_TCPIP_IP_ADDR0_OFFSET			(ROM_NEXT_OFFSET_AFTER_COM_SETTING)
#define ROM_TCPIP_IP_ADDR1_OFFSET			(ROM_TCPIP_IP_ADDR0_OFFSET + ROM_TCPIP_IP_ADDR_PARTIAL_LENGTH)
#define ROM_TCPIP_IP_ADDR2_OFFSET			(ROM_TCPIP_IP_ADDR1_OFFSET + ROM_TCPIP_IP_ADDR_PARTIAL_LENGTH)
#define ROM_TCPIP_IP_ADDR3_OFFSET			(ROM_TCPIP_IP_ADDR2_OFFSET + ROM_TCPIP_IP_ADDR_PARTIAL_LENGTH)
//------ 4 x 1 byte = 4 bytes

#define ROM_TCPIP_SUBNET_MASK0_OFFSET		(ROM_TCPIP_IP_ADDR3_OFFSET + ROM_TCPIP_IP_ADDR_PARTIAL_LENGTH)
#define ROM_TCPIP_SUBNET_MASK1_OFFSET		(ROM_TCPIP_SUBNET_MASK0_OFFSET + ROM_TCPIP_SUBNET_MASK_PARTIAL_LENGTH)
#define ROM_TCPIP_SUBNET_MASK2_OFFSET		(ROM_TCPIP_SUBNET_MASK1_OFFSET + ROM_TCPIP_SUBNET_MASK_PARTIAL_LENGTH)
#define ROM_TCPIP_SUBNET_MASK3_OFFSET		(ROM_TCPIP_SUBNET_MASK2_OFFSET + ROM_TCPIP_SUBNET_MASK_PARTIAL_LENGTH)
//------ 4 x 1 byte = 4 bytes

#define ROM_TCPIP_GATEWAY0_OFFSET			(ROM_TCPIP_SUBNET_MASK3_OFFSET + ROM_TCPIP_SUBNET_MASK_PARTIAL_LENGTH)
#define ROM_TCPIP_GATEWAY1_OFFSET			(ROM_TCPIP_GATEWAY0_OFFSET + ROM_TCPIP_GATEWAY_PARTIAL_LENGTH)
#define ROM_TCPIP_GATEWAY2_OFFSET			(ROM_TCPIP_GATEWAY1_OFFSET + ROM_TCPIP_GATEWAY_PARTIAL_LENGTH)
#define ROM_TCPIP_GATEWAY3_OFFSET			(ROM_TCPIP_GATEWAY2_OFFSET + ROM_TCPIP_GATEWAY_PARTIAL_LENGTH)
//------ 4 x 1 byte = 4 bytes

#define ROM_TCPIP_DNS_SERVER0_OFFSET		(ROM_TCPIP_GATEWAY3_OFFSET + ROM_TCPIP_GATEWAY_PARTIAL_LENGTH)
#define ROM_TCPIP_DNS_SERVER1_OFFSET		(ROM_TCPIP_DNS_SERVER0_OFFSET + ROM_TCPIP_DNS_SERVER_PARTIAL_LENGTH)
#define ROM_TCPIP_DNS_SERVER2_OFFSET		(ROM_TCPIP_DNS_SERVER1_OFFSET + ROM_TCPIP_DNS_SERVER_PARTIAL_LENGTH)
#define ROM_TCPIP_DNS_SERVER3_OFFSET		(ROM_TCPIP_DNS_SERVER2_OFFSET + ROM_TCPIP_DNS_SERVER_PARTIAL_LENGTH)
//------ 4 x 1 byte =  4 bytes

#define ROM_TCPIP_ALT_DNS_SERVER0_OFFSET	(ROM_TCPIP_DNS_SERVER3_OFFSET + ROM_TCPIP_DNS_SERVER_PARTIAL_LENGTH)
#define ROM_TCPIP_ALT_DNS_SERVER1_OFFSET	(ROM_TCPIP_ALT_DNS_SERVER0_OFFSET + ROM_TCPIP_DNS_SERVER_PARTIAL_LENGTH)
#define ROM_TCPIP_ALT_DNS_SERVER2_OFFSET	(ROM_TCPIP_ALT_DNS_SERVER1_OFFSET + ROM_TCPIP_DNS_SERVER_PARTIAL_LENGTH)
#define ROM_TCPIP_ALT_DNS_SERVER3_OFFSET	(ROM_TCPIP_ALT_DNS_SERVER2_OFFSET + ROM_TCPIP_DNS_SERVER_PARTIAL_LENGTH)
//------ 4 x 1 byte =  4 bytes

#define ROM_TCPIP_CONF_AUTOMANUAL_OFFSET	(ROM_TCPIP_ALT_DNS_SERVER3_OFFSET + ROM_TCPIP_DNS_SERVER_PARTIAL_LENGTH)
//------ 1 x 1 byte = 1 byte
//! @}

#define ROM_TCPIP_SETTING_SIZE		21

/* Next Offset after TCP/IP setting. */
#define ROM_NEXT_OFFSET_AFTER_TCPIP_SETTING		(ROM_NEXT_OFFSET_AFTER_COM_SETTING + ROM_TCPIP_SETTING_SIZE)

/* End------------------------------------------ Hardware Configuration --------------------------------- */


#define ROM_HARDWARE_SIZE		(ROM_NEXT_OFFSET_AFTER_TCPIP_SETTING)

#if ROM_HARDWARE_SIZE > 1024
#error ROM of Harware is exceed!
#endif

#endif /* CONFIG_ROM_HW_H_ */
